(1) Field of the Invention
The invention relates to a method of fabricating both 3 and 5 volt CMOS transistors in the fabrication of integrated circuits, and more particularly, to a method of fabricating both 3 and 5 volt CMOS transistors simultaneously by depressing or enhancing gate silicon oxide growth in the fabrication of integrated circuits.
(2) Description of the Prior Art
The gate oxide thickness is the major issue in terms of reliability considerations in mixing 3 and 5 volt transistors in one device. A thin gate oxide of about 90 Angstroms is grown in the conventional 3 V, 0.6 micron process while a thick gate oxide of about 140 Angstroms is grown in the conventional 5 V, 0.6 micron process. The thick gate oxide under a 3 V transistor will cause poor device performance and speed while a thin gate oxide under a 5 V transistor will cause a reliability problem in the gate oxide film.
U.S. Pat. No. 4,716,126 to Cogan shows the use of nitrogen implantation into silicon surfaces and annealing wherein the nitrogen is an oxidation retardant. U.S. Pat. No. 4,948,742 to Nishimura et al shows ion implantation of nitrogen and oxygen into the depth of a silicon body to form dielectric regions within the silicon body.